The present invention relates to a non-volatile semiconductor memory device, having an enhanced margin of the implanted ion passing through an electrode, and excellent covering power (that is, surface smoothness) of an embedded layer deposited in a groove within a field oxide region distributed at both a memory cell area and a peripheral circuit area. The present invention also relates to a method for manufacturing the same.
A memory device retaining memories recorded therein after its electric power is switched off is generally called a non-volatile semiconductor memory device, including, for example, a ROM (Read Only Memory) and a PROM (Programmable ROM) and the like. The ROM does not allow a user to write another data therein, in addition to the data which had been written by a manufacturer. On the other hand, the PROM permits a user to write another data. The PROM generally classifies into three types: one in which the data is rewritten only once; an EPROM (Electrically Programmable ROM) in which the data is possible to erase by exposing to ultraviolet light and to further rewrite them any number of times; and an EEPROM (Electrically Erasable and Programmable ROM) in which the data is possible to erase by supplying with an electric signal and to further rewrite them any number of times. For the EEPROM, the erasion may be conducted by applying a high-voltage signal between its control gates.
The non-volatile semiconductor memory device generally includes a cell array region containing a memory cell area, and a peripheral circuit region distributed around the cell array region. The memory cell area in the cell array region comprises a floating gate for storing the data and a control gate for controlling the floating gate.
In general, the non-volatile semiconductor memory device is manufactured by a conventional method including steps as shown in FIGS. 5 and 6, as explained as follows:
(1) First, a field oxide region 2 is formed in a recess on a surface of a semiconductor substrate 1, and then a first insulator layer 61 is deposited over the whole substrate 1 (FIG. 5 (1)).
(2) A film-forming material for a floating gate is deposited over the whole substrate 1 and subjected to any lithographic processes to form a floating gate 4 (FIG. 5 (2)).
(3) An interlaminar insulator layer 62 for separating the floating gate from a control gate 5 (as explained hereinafter) is formed on the whole substrate 1 containing the floating gate 4, and subsequently covered with a material for forming a control gate 5 (FIG. 5 (3)).
(4) A control gate 6 is formed by any lithographic processes before the film-forming material for the floating gate 4 remaining between the control gates 6 is removed to form a groove 10 in the field oxide region 2 between the floating gates 4 (that is, between the control gates 6) (FIG. 6).
After the step (4), the following procedures are continued to form an electrode.
(5) On the whole substrate, tetraethylorthosilicate (abbreviated as TEOS) is generally deposited as an embedded layer 3 (FIG. 7 (i)).
(6) The embedded layer 3 is then etched back (FIG. 7 (ii)).
(7) An ion implantation into an electrode is conducted.
(8) Both the embedded layer 3 and field oxide region 2 remaining at a source area are etched to perfectly remove (FIG. 7 (iii)). An etching rate is determined by defining as an endpoint a time taken to perfectly remove the thickest parts of both the embedded layer and the field oxide region. After the etching step, ion implanting is conducted.
In general, an interlayer is then deposited on the resulting electrode after the ion implanting.
However, the embedded layer deposited on the electrode in the above way was adversely affected by an asperity of a surface of an underlayer. For example, the embedded layer bulged at a convex part of the underlayer, such as a part around a top of an inwall of the groove 10 and the like, and it was significantly concave at a fallen part of the underlayer, such as a part above an opening of the groove 10, as shown in FIG. 7 (i). Thus, the embedded layer significantly resulted in the poor surface smoothness.
Therefore, after the step (6) in the conventional method, the embedded layer 3 generally remains in an extremely thin form at a center of the groove, or a part of the bottom of the groove uncovered with the embedded layer 3 was optionally exposed, as shown in FIG. 7 (ii). When the remaining embedded layer 3 was optionally subjected to the etching step (8) as explained above to perfectly remove, the part of the substrate 1 which was not covered with the embedded layer 3 would be overetched, as shown by number 20 in FIG. 7 (iii). In the conventional semiconductor memory device, when some problems such as the increased electric resistance and the like occurred, the overetched area 20 was generated on the surface of the substrate.
Alternatively, when the memory area or the source area is formed, the embedded layer and the field oxide region remains with neither ion implanting nor etching (as explained in the above steps (6) and (7)) after the above step (5), and then they are further covered with the interlayer. However, since the residual embedded layer and the field oxide region had the asperity on their surface as explained above, the interlayer further deposited thereon also resulted in the poor surface smoothness (that is, the poor covering power).
Accordingly, one purpose of the present invention is to overcome the above problems and to enhance a margin of implanted ion passing through the electrode, as well as to improve the covering power (the surface smoothness) of the interlayer further deposited in and above the groove formed within the field oxide region distributed at both the memory cell area and the peripheral circuit area.
Accordingly, the present invention provides a non-volatile semiconductor memory device, comprising a semiconductor substrate having a recess pattern on a surface thereof, a field oxide region formed in the recess pattern, and on the surface of the semiconductor substrate, a first insulator layer, a floating gate-electrode layer, a second insulator layer and a control gate-electrode layer which are deposited after the formation of the field oxide region, wherein the floating gate-electrode layer is formed adjacent to the field oxide region having a groove therein, followed by depositing an embedded layer over the whole surface of the semiconductor substrate, including the groove, and then etching back, characterized by that a width (w) at the bottom of the groove is adjusted to be at most twice larger than a distance (t) between the lowest level of the surface of the embedded layer in the groove and each end of the bottom of the groove.
For the non-volatile semiconductor memory device of the present invention, the embedded layer is deposited over the whole surface of the semiconductor substrate, including the groove, and remains in and above the groove even after the etching-back. The embedded layer may be deposited in and above the groove, more preferably up to the same level as a top of the inwall of the groove. Particularly, the inwall of the groove tilts so as to have a wider width between the top of the inwall of the groove than the width of the bottom of the groove.
An example of a suitable material for forming the embedded layer in the non-volatile semiconductor memory device of the present invention may be selected from the group consisting of high density plasma CVD film (abbreviated as HDP, hereinafter), both boron and phosphorous-doped tetraethyl orthosilicate (abbreviated as BPTEOS), boron-doped tetraethyl orthosilicate (abbreviated as BTEOS) and phosphorous-doped tetraethyl orthosilicate (abbreviated as PTEOS).
Alternatively, the present invention further provides a method for manufacturing the non-volatile semiconductor memory device, comprising steps of providing a recess pattern on a surface of a semiconductor substrate to form a field oxide region in the recess pattern, depositing a first insulator layer and a floating gate-electrode layer on the surface of a semiconductor substrate and etching them to form a floating gate, depositing a second insulator layer and a control gate-electrode layer over the whole surface of the semiconductor substrate and etching them to form a control gate, and then removing the residual floating gate-electrode layer on an electrode region to form a groove in the field oxide region, further comprising a step of depositing an embedded layer over the whole surface of the semiconductor substrate, including the groove, followed by etching back to be a width (w) at the bottom of the groove at most twice larger than a distance (t) between the lowest level of the surface of the embedded layer in the groove and each end of the bottom of the groove, characterized by that the step of etching a memory cell in a cell array region is conducted apart from the process for a peripheral circuit region distributed around the cell array region, where does not essentially need the etching step.